1. Technical Field
The inventive concept relates to a semiconductor integrated apparatus, and more particularly, to a fabrication method of a semiconductor apparatus
2. Related Art
Various researches on improvement of integration density in semiconductor memory apparatuses have been progressed. As an example, there are vertical diodes or vertical transistors.
In vertical switching devices, pillars have to be formed to have a sufficient thickness to improve off-current characteristic or an effective channel length. However, the high height of the pillar causes an aspect ratio to be increased so that the process of forming the device has difficulty and leaning of the pillar occurs.
Thus, horizontal channel transistors have been suggested and will be described with reference FIGS. 1 to 6.
FIGS. 1 to 6 are cross-sectional views illustrating a method of fabricating a related semiconductor apparatus.
First, as illustrated in FIG. 1, a common source region 103 having a predetermined depth is formed in an upper surface of a semiconductor substrate 101. The common source region 103 may be formed, for example, through N+ type impurity implantation. Further, the common source region 103 may be formed after an active region is formed in a subsequent process.
Subsequently, a sacrificial layer 105 having a predetermined thickness and a first semiconductor layer 107 having a predetermined thickness are sequentially formed on the semiconductor substrate 101 including the common source region 103. The sacrificial layer 105 and the first semiconductor layer 107 includes semiconductor material layers having different etch selectivity from each other. For example, the sacrificial layer 105 may include silicon germanium (Site) and the first semiconductor layer 107 may include silicon (Si). Both of the sacrificial layer 105 and the first semiconductor layer 107 may be formed through an epitaxial growth method to have a perfect crystalline state.
As illustrated in FIG. 2, a photoresist pattern (not shown) is formed on a predetermined region of the first semiconductor layer 107, and the first semiconductor layer 107 and the sacrificial layer 105 are patterned in the same shape of the photoresist pattern to form a hole 109 exposing a surface of the common source region 103.
After the hole 109 is formed, a native oxide layer is completely removed and a heat treatment is performed at a predetermined temperature in an ambient of hydrogen. When the heat treatment is performed at a predetermined temperature in an ambient of hydrogen, the first semiconductor layer 107 is flowed to be filled in the hole, and a second semiconductor layer 111 is formed as illustrated in FIG. 3.
After the second semiconductor layer 111 is formed, a hard mask (not shown) is formed in a direction (the same direction as a direction of the device illustrated in FIG. 3) perpendicular to a formation direction of a gate line to be formed in a subsequent process, and the second semiconductor layer 111 and the sacrificial layer 105 are patterned to confine an active region. As described above, the common source region may be formed after the confining of the active region.
When an active region ACT is defined, as illustrated in FIG. 4, the sacrificial layer 105 is removed along the exposed surface, and an insulating layer 113 is formed in a space in which the sacrificial layer is removed to form a local silicon-on-insulator (SOI) structure. The semiconductor substrate as illustrated in FIG. 5 may be referred to as a local SOI substrate or a local SOI wafer.
As illustrated in FIG. 6, a word line 115 is formed on the active region ACT through a gate formation process and impurities are implanted into the active region ACT at both sides of the word line 115 to form a source region C and a drain region D. At this time, the source region S is a region electrically connected to the semiconductor substrate 101, specifically, the common source region 103, and the drain region D is a region on the insulating layer 113.
As described above, the fabricating of the horizontal transistor flows the first semiconductor layer to form the second semiconductor layer 111. At this time, a flowing state of the first semiconductor layer 107 may be changed according to a surface state of the semiconductor substrate 101, a pattern density, and a line/spacer pattern size. Therefore, the active region may be formed to have a uniform thickness.
Further, when the flowing process of the first semiconductor layer 107 is unstable, electrical defects occur. Since lattice constants of the first semiconductor layer 107 and the sacrificial layer 105 are different, lattice defects may occur in the epitaxial growth process for forming the first semiconductor layer 107 on the sacrificial layer 105 or in the heat treatment process for flowing the first semiconductor layer.
The insulating layer 113 buried below the active region ACT after the removing of the sacrificial layer 105 may include an insulating material such as a spin on dielectric (SOD) which is easily etched in a wet etchant. Therefore, when forming a word line 115 in a subsequent process, controlling of a width in the word line 115 is difficult since etch characteristic of a structure of the word line 115 is different from that of the insulating layer.
Further, the SOT substrate fabricated through the above-described method is high-priced and thus costs of SOT-based memory devices and apparatuses are also increased.